We introduce Design2Vec, a representation learning approach to learn semantic abstractions of hardware designs at the Register Transfer Level (RTL) for scaling the complexity of design verification. The key idea of our approach is to design a Graph convolution based neural architecture that embeds RTL syntax and semantics and pretrain it to learn the design state space. We train the model on the task of predicting coverage points in the design, given an input parameterized test. Our experimental results demonstrate that Design2Vec outperforms several baseline approaches that do not incorporate the RTL semantics and it can be used to generate instantaneous coverage predictions compared to nightly simulation times. We then present an approach to use Design2Vec to automatically generate new inputs for unseen coverage locations in the design. Moreover, the tests generated using Design2Vec result in coverage of design points that are difficult to cover for design verification experts using the current manual practices in test generation. We demonstrate that Design2Vec is able to scale to the a contemporary industrial scale chip design.